Questions?
[x] Content Type
Patent Filings

[x] SRC Program
GRC

Center
TxACE 1

Thrust/Theme
AMS-CSD – Analog/Mixed-Signal Ci... 1

1 through 1 of 1 similar documents, best matches first.   
1: Dual Feeback Loops for Integrated Voltage and Clock Regulation...
Dual Feeback Loops for Integrated Voltage and Clock Regulation Application Type: Utility Patent Number: 11277141 Country: United States Status: Filed on 4-Mar-2021, Issued on ...
URL: https://www.src.org/library/patent/p1955/
Modified: 2022-03-15 - 23KB
Find Similar Documents