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GRC Science Area
CADTS – Computer Aided Design & Test Sciences
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83 similar documents, best matches first. |
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- 1:
Method and System for Synthesizing Relative Timing Constraints...
- Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design to Facilitate Timing Verification Application Type: Continuation Patent Number: ...
URL: https://www.src.org/library/patent/p1354/
Modified: 2012-11-27 - 24KB Find Similar Documents
- 2:
Method and System for Synthesizing Relative Timing Constraints...
- Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design to Facilitate Timing Verification Application Type: Utility Patent Number: 8239796 ...
URL: https://www.src.org/library/patent/p1202/
Modified: 2012-08-07 - 24KB Find Similar Documents
- 3:
Methods, Apparatus and Computer Program products for Synthesizing...
- Methods, Apparatus and Computer Program products for Synthesizing Integrated Circuits with Electrostatic Discharge Capability and Correcting Ground Rule Faults Therein Application ...
URL: https://www.src.org/library/patent/p0049/
Modified: 1998-08-18 - 27KB Find Similar Documents
- 4:
Final Report - Workshop on Failure and Uncertainty in Mixed-Signal...
- National Science Foundation Workshop on Failure and Uncertainty in Mixed-Signal Circuits and Systems Arlington, Virginia July 8-9, 2010 Principal Investigators: Ralph Cavin, ...
URL: https://www.src.org/calendar/e004025/final-report.pdf
Modified: 2011-06-01 - 914KB Find Similar Documents
- 5:
Multi-Layer Integrated Circuits Having Isolation Cells for Layer...
- Multi-Layer Integrated Circuits Having Isolation Cells for Layer Testing and Related Methods Application Type: Continuation (in part) Patent Number: 10838003 Country: United States ...
URL: https://www.src.org/library/patent/p1826/
Modified: 2020-11-17 - 25KB Find Similar Documents
- 6:
Multi-Layer Integrated Circuits Having Isolation Cells for Layer...
- Multi-Layer Integrated Circuits Having Isolation Cells for Layer Testing and Related Methods Application Type: Utility Patent Number: 10338133 Country: United States Status: Filed ...
URL: https://www.src.org/library/patent/p1639/
Modified: 2019-07-02 - 25KB Find Similar Documents
- 7:
Testing Monolithic Three Dimensional Integrated Circuits (Patent...
- Testing Monolithic Three Dimensional Integrated Circuits Application Type: Utility Patent Number: 10775429 Country: United States Status: Filed on 2-Nov-2017, Issued on 15-Sep-2020 ...
URL: https://www.src.org/library/patent/p1746/
Modified: 2020-09-15 - 25KB Find Similar Documents
- 8:
ESD/EOS Protection Circuits for Integrated Circuits (Patent P0074...
- ESD/EOS Protection Circuits for Integrated Circuits Application Type: Utility Patent Number: 5450267 Country: United States Status: Filed on 31-Mar-1993, Issued on 12-Sep-1995, ...
URL: https://www.src.org/library/patent/p0074/
Modified: 1995-09-12 - 25KB Find Similar Documents
- 9:
Source Contact Placement for Efficient ESD/EOS Protection in...
- Source Contact Placement for Efficient ESD/EOS Protection in Grounded Substrate MOS Integrated Circuit Application Type: Utility Patent Number: 5404041 Country: United States ...
URL: https://www.src.org/library/patent/p0067/
Modified: 1995-04-04 - 25KB Find Similar Documents
- 10:
Software-Based Self-Test and Diagnosis Using on-Chip Memory ...
- Software-Based Self-Test and Diagnosis Using on-Chip Memory Application Type: Divisional Patent Number: 10788532 Country: United States Status: Filed on 30-Nov-2017, Issued on ...
URL: https://www.src.org/library/patent/p1753/
Modified: 2020-09-29 - 26KB Find Similar Documents
- 11:
Software-Based Self-Test and Diagnosis Using on-Chip Memory ...
- Software-Based Self-Test and Diagnosis Using on-Chip Memory Application Type: Divisional Patent Number: 10845416 Country: United States Status: Filed on 30-Nov-2017, Issued on ...
URL: https://www.src.org/library/patent/p1752/
Modified: 2020-11-24 - 26KB Find Similar Documents
- 12:
Software-Based Self-Test and Diagnosis Using On-Chip Memory ...
- Software-Based Self-Test and Diagnosis Using On-Chip Memory Application Type: Utility Patent Number: 9864007 Country: United States Status: Filed on 30-Apr-2014, Issued on ...
URL: https://www.src.org/library/patent/p1457/
Modified: 2018-01-09 - 25KB Find Similar Documents
- 13:
Signal Tracing Using On-Chip Memory For In-System Post-Fabrication...
- Signal Tracing Using On-Chip Memory For In-System Post-Fabrication Debug Application Type: Utility Patent Number: 9720036 Country: United States Status: Filed on 18-Aug-2014, ...
URL: https://www.src.org/library/patent/p1495/
Modified: 2017-08-01 - 23KB Find Similar Documents
- 14:
Signal Tracing using ON-Chip Memory for In-System Post-Fabrication...
- Signal Tracing using ON-Chip Memory for In-System Post-Fabrication Debug Application Type: Continuation Patent Number: 10732221 Country: United States Status: Filed on 26-Jun-2017, ...
URL: https://www.src.org/library/patent/p1733/
Modified: 2020-08-04 - 24KB Find Similar Documents
- 15:
Non-Invasive Pre-Bond TSV TestUsing Ring Oscillators and Multiple...
- Non-Invasive Pre-Bond TSV TestUsing Ring Oscillators and Multiple Voltage Levels Application Type: Utility Patent Number: 9478720 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1392/
Modified: 2016-11-01 - 24KB Find Similar Documents
- 16:
Non-Invasive Pre-Bond TSV Test using Ring Oscillators and Multiple...
- Non-Invasive Pre-Bond TSV Test using Ring Oscillators and Multiple Voltage Levels Application Type: Continuation Patent Number: 10444279 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1635/
Modified: 2019-10-15 - 23KB Find Similar Documents
- 17:
Method and System for Performing Global Routing on an Integrated...
- Method and System for Performing Global Routing on an Integrated Circuit Design Application Type: Utility Patent Number: 7661085 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1032/
Modified: 2010-02-09 - 22KB Find Similar Documents
- 18:
Built-in Current Testing of Integrated Circuits (Patent P0109...
- Built-in Current Testing of Integrated Circuits Application Type: Utility Patent Number: 5025344 Country: United States Status: Filed on 22-Feb-1990, Issued on 18-Jun-1991, Patent ...
URL: https://www.src.org/library/patent/p0109/
Modified: 1991-06-18 - 22KB Find Similar Documents
- 19:
Method for Testing Analog and Mixed-Signal Circuits Using Functionally...
- Method for Testing Analog and Mixed-Signal Circuits Using Functionally Related Excitations and Functionally Related Measurements Application Type: Utility Patent Number: 7129734 ...
URL: https://www.src.org/library/patent/p0458/
Modified: 2006-10-31 - 25KB Find Similar Documents
- 20:
Method and Architecture for Pre-bond Probing of TSVs in 3D Stacked...
- Method and Architecture for Pre-bond Probing of TSVs in 3D Stacked Integrated Circuits Application Type: Utility Patent Number: 8775108 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1291/
Modified: 2014-07-08 - 22KB Find Similar Documents
- 21:
Power Switch Design and Method for Reducing Leakage Power in...
- Power Switch Design and Method for Reducing Leakage Power in Low-Power Integrated Circuits Application Type: Utility Patent Number: 8373493 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1239/
Modified: 2013-02-12 - 22KB Find Similar Documents
- 22:
Method of placing source contacts for efficient EDS\EOS protection...
- Method of placing source contacts for efficient EDS\EOS protection in grounded substrate MOS integrated circuit Application Type: Divisional Patent Number: 5468667 Country: United ...
URL: https://www.src.org/library/patent/p0373/
Modified: 1995-11-21 - 22KB Find Similar Documents
- 23:
System and Method to Test Integrated Circuits on a Wafer (Patent...
- System and Method to Test Integrated Circuits on a Wafer Application Type: Utility Patent Number: 7325180 Country: United States Status: Filed on 26-Nov-2003, Issued on ...
URL: https://www.src.org/library/patent/p0413/
Modified: 2008-01-29 - 22KB Find Similar Documents
- 24:
Method and Apparatus For Rapidly Modeling and Simulating Intra...
- Method and Apparatus For Rapidly Modeling and Simulating Intra-Die Statistical Variations in Integrated Circuits using Compressed Parameter Models Application Type: Utility Patent ...
URL: https://www.src.org/library/patent/p1160/
Modified: 2012-10-16 - 24KB Find Similar Documents
- 25:
Methods for Characterizing, Generating Test Sequences for, and...
- Methods for Characterizing, Generating Test Sequences for, and Simulating Integrated Circuit Faults Using Fault Tuples and Related Systems and Computer Program Products Application ...
URL: https://www.src.org/library/patent/p0228/
Modified: 2004-12-28 - 22KB Find Similar Documents
- 26:
Method for Testing Analog and Mixed-Signal Circuits Using Dynamic...
- Method for Testing Analog and Mixed-Signal Circuits Using Dynamic Element Matching for Source Linearization Application Type: Utility Patent Number: 7587647 Country: United States ...
URL: https://www.src.org/library/patent/p0468/
Modified: 2009-09-08 - 23KB Find Similar Documents
- 27:
SRC/NSF Design Forum - Position Statement
- A Position Statement in the Forum on Future Directions for Design Automation Research Jason Cong UCLA Computer Science Department http://cadlab.cs.ucla.edu/~cong There are many ...
URL: https://www.src.org/...764/jason-cong-position-statement.pdf
Modified: 2011-08-02 - 35KB Find Similar Documents
- 28:
Retiming-Based Design Flow for Delay Recovery on Inter-Die Paths...
- Retiming-Based Design Flow for Delay Recovery on Inter-Die Paths in 3D ICs Application Type: Utility Patent Number: 8832608 Country: United States Status: Filed on 17-Jun-2013, ...
URL: https://www.src.org/library/patent/p1411/
Modified: 2014-09-09 - 22KB Find Similar Documents
- 29:
Method, Apparatus and Computer Program Product for Determining...
- Method, Apparatus and Computer Program Product for Determining a Frequency Domain Response of a Nonlinear Microelectronic Circuit Application Type: Utility Patent Number: 5663890 ...
URL: https://www.src.org/library/patent/p0014/
Modified: 1997-09-02 - 24KB Find Similar Documents
- 30:
Scan Test of Die Logic in 3D ICs Using TSV Probing (Patent P1368...
- Scan Test of Die Logic in 3D ICs Using TSV Probing Application Type: Utility Patent Number: 8782479 Country: United States Status: Filed on 1-Nov-2012, Issued on 15-Jul-2014, ...
URL: https://www.src.org/library/patent/p1368/
Modified: 2014-07-15 - 22KB Find Similar Documents
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83 similar documents, best matches first. |
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