Questions?
[x] SRC Program
GRC

[x] GRC Science Area
CADTS – Computer Aided Design & Test Sciences

Content Type
Patent Filings 74
Events 8
Other 1

Year
2011 8

Center
TxACE 3
C2S2 2
ACE4S 1
CAIST 1
CDADIC 1
CEMPI 1
CHIRP 1
EBSM 1
GSRC 1
IPC 1
NCRC 1

Thrust/Theme
TT – Test & Testability 34
LPD – Logic & Physical Design 19
CADT – Computer-Aided Design and... 10
DesTech – Design Techniques 6
Physical Design 5
TechCAD – Technology CAD 4
VER – Verification 4
DV – Design Verification 2
DesSyn – Design Synthesis 2
I3T – Innovative and Intelligent... 2
Synthesis & Verification 2
ADS – Alternative Device Structu... 1
AIHW – Artificial Intelligence H... 1
AMS – Analog and Mixed-Signal De... 1
AMS-CSD – Analog/Mixed-Signal Ci... 1
AdvTech – Advanced Technology 1
Advanced Bipolar SOI-MOS Transis... 1
Advanced Devices 1
Advanced Devices & Technologies 1
Advanced Technology Option 1
Analysis Design & Simulation 1
BEP – Back End Processes 1
Back End Processes 1
C&S – Controls and Sensing 1
CD – Circuit Design 1
CFM&TCM – CFM & Total Chemical M... 1
CM – Compact Modeling 1
CSR – Cross-Disciplinary Semicon... 1
Contamination Control 1
Cost Reduction 1
DCMOS – Digital CMOS Technologie... 1
DE – Design Environment 1
DSMS – Device Sciences Modeling ... 1
Defect Reduction 1
Deposition 1
Doping Technologies 1
EP3C – Efficiency and Performanc... 1
ESH – Environment Safety and Hea... 1
Equip Automation & Process Contr... 1
Equip – Equipment 1
Equip. Auto. and Process Control 1
FACSYS – Factory Systems 1
FAM – Factory Automation & Manag... 1
FEOL – FEOL Processes 1
FacOps – Factory Operations 1
Factory Systems 1
Front End Processes 1
HWS – Hardware Security 1
Heat Signal & Power Distribution 1
Heat Signal Power 1
ISD – Integrated System Design 1
Interconnect Architecture 1
LMD – Logic and Memory Devices 1
Lithography 1
Logic Design 1
Logistics & Modeling/Simulation 1
MT – Memory Technologies 1
MTMP – Metrology Tools Matls & P... 1
Masks 1
Materials 1
Materials & Measurements 1
Metrology 1
Modeling & Simulation 1
Modeling & TCAD 1
Multi-level Interconnect 1
NCR – Non-Classical CMOS Researc... 1
NEM – Nanoengineered Materials 1
NMP – Nanomanufacturing Material... 1
PAT – Patterning 1
PKG – Packaging 1
PMM – Packaging Materials and Me... 1
PMS – Packaging Modeling and Sim... 1
PS/E – Process Simplification/En... 1
Package & Electrical Design 1
Package Reliability 1
Packaging & Interconnect Systems 1
Packaging Materials Interfaces 1
Pat(MPS) – Patterning 1
PatMat – Patterning Materials 1
PatSys – Patterning Systems 1
PhyDes – Physical Design 1
Plasma Etch 1
Process Architecture 1
Processes – Processes 1
Quality & Reliability 1
Rapid Yield Learning 1
Reliability 1
Resist 1
SLD – System Level Design 1
SemiSynBio – Semiconductor Synth... 1
Semiconductor Modeling & Simulat... 1
Signal/Power Management 1
Substrates 1
TCAD-MBPS 1
TM – Thermal Management 1

1 through 30 of 83 similar documents, best matches first.   
Results by:Thunderstone Page: 1 2 3 next >>
1: Method and System for Synthesizing Relative Timing Constraints...
Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design to Facilitate Timing Verification Application Type: Continuation Patent Number: ...
URL: https://www.src.org/library/patent/p1354/
Modified: 2012-11-27 - 24KB
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2: Method and System for Synthesizing Relative Timing Constraints...
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URL: https://www.src.org/library/patent/p1202/
Modified: 2012-08-07 - 24KB
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3: Methods, Apparatus and Computer Program products for Synthesizing...
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URL: https://www.src.org/library/patent/p0049/
Modified: 1998-08-18 - 27KB
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4: pdfFinal Report - Workshop on Failure and Uncertainty in Mixed-Signal...
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URL: https://www.src.org/calendar/e004025/final-report.pdf
Modified: 2011-06-01 - 914KB
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5: Multi-Layer Integrated Circuits Having Isolation Cells for Layer...
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URL: https://www.src.org/library/patent/p1826/
Modified: 2020-11-17 - 25KB
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6: Multi-Layer Integrated Circuits Having Isolation Cells for Layer...
Multi-Layer Integrated Circuits Having Isolation Cells for Layer Testing and Related Methods Application Type: Utility Patent Number: 10338133 Country: United States Status: Filed ...
URL: https://www.src.org/library/patent/p1639/
Modified: 2019-07-02 - 25KB
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7: Testing Monolithic Three Dimensional Integrated Circuits (Patent...
Testing Monolithic Three Dimensional Integrated Circuits Application Type: Utility Patent Number: 10775429 Country: United States Status: Filed on 2-Nov-2017, Issued on 15-Sep-2020 ...
URL: https://www.src.org/library/patent/p1746/
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8: ESD/EOS Protection Circuits for Integrated Circuits (Patent P0074...
ESD/EOS Protection Circuits for Integrated Circuits Application Type: Utility Patent Number: 5450267 Country: United States Status: Filed on 31-Mar-1993, Issued on 12-Sep-1995, ...
URL: https://www.src.org/library/patent/p0074/
Modified: 1995-09-12 - 25KB
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9: Source Contact Placement for Efficient ESD/EOS Protection in...
Source Contact Placement for Efficient ESD/EOS Protection in Grounded Substrate MOS Integrated Circuit Application Type: Utility Patent Number: 5404041 Country: United States ...
URL: https://www.src.org/library/patent/p0067/
Modified: 1995-04-04 - 25KB
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10: Software-Based Self-Test and Diagnosis Using on-Chip Memory ...
Software-Based Self-Test and Diagnosis Using on-Chip Memory Application Type: Divisional Patent Number: 10788532 Country: United States Status: Filed on 30-Nov-2017, Issued on ...
URL: https://www.src.org/library/patent/p1753/
Modified: 2020-09-29 - 26KB
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11: Software-Based Self-Test and Diagnosis Using on-Chip Memory ...
Software-Based Self-Test and Diagnosis Using on-Chip Memory Application Type: Divisional Patent Number: 10845416 Country: United States Status: Filed on 30-Nov-2017, Issued on ...
URL: https://www.src.org/library/patent/p1752/
Modified: 2020-11-24 - 26KB
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12: Software-Based Self-Test and Diagnosis Using On-Chip Memory ...
Software-Based Self-Test and Diagnosis Using On-Chip Memory Application Type: Utility Patent Number: 9864007 Country: United States Status: Filed on 30-Apr-2014, Issued on ...
URL: https://www.src.org/library/patent/p1457/
Modified: 2018-01-09 - 25KB
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13: Signal Tracing Using On-Chip Memory For In-System Post-Fabrication...
Signal Tracing Using On-Chip Memory For In-System Post-Fabrication Debug Application Type: Utility Patent Number: 9720036 Country: United States Status: Filed on 18-Aug-2014, ...
URL: https://www.src.org/library/patent/p1495/
Modified: 2017-08-01 - 23KB
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14: Signal Tracing using ON-Chip Memory for In-System Post-Fabrication...
Signal Tracing using ON-Chip Memory for In-System Post-Fabrication Debug Application Type: Continuation Patent Number: 10732221 Country: United States Status: Filed on 26-Jun-2017, ...
URL: https://www.src.org/library/patent/p1733/
Modified: 2020-08-04 - 24KB
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15: Non-Invasive Pre-Bond TSV TestUsing Ring Oscillators and Multiple...
Non-Invasive Pre-Bond TSV TestUsing Ring Oscillators and Multiple Voltage Levels Application Type: Utility Patent Number: 9478720 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1392/
Modified: 2016-11-01 - 24KB
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16: Non-Invasive Pre-Bond TSV Test using Ring Oscillators and Multiple...
Non-Invasive Pre-Bond TSV Test using Ring Oscillators and Multiple Voltage Levels Application Type: Continuation Patent Number: 10444279 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1635/
Modified: 2019-10-15 - 23KB
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17: Method and System for Performing Global Routing on an Integrated...
Method and System for Performing Global Routing on an Integrated Circuit Design Application Type: Utility Patent Number: 7661085 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1032/
Modified: 2010-02-09 - 22KB
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18: Built-in Current Testing of Integrated Circuits (Patent P0109...
Built-in Current Testing of Integrated Circuits Application Type: Utility Patent Number: 5025344 Country: United States Status: Filed on 22-Feb-1990, Issued on 18-Jun-1991, Patent ...
URL: https://www.src.org/library/patent/p0109/
Modified: 1991-06-18 - 22KB
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19: Method for Testing Analog and Mixed-Signal Circuits Using Functionally...
Method for Testing Analog and Mixed-Signal Circuits Using Functionally Related Excitations and Functionally Related Measurements Application Type: Utility Patent Number: 7129734 ...
URL: https://www.src.org/library/patent/p0458/
Modified: 2006-10-31 - 25KB
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20: Method and Architecture for Pre-bond Probing of TSVs in 3D Stacked...
Method and Architecture for Pre-bond Probing of TSVs in 3D Stacked Integrated Circuits Application Type: Utility Patent Number: 8775108 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1291/
Modified: 2014-07-08 - 22KB
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21: Power Switch Design and Method for Reducing Leakage Power in...
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URL: https://www.src.org/library/patent/p1239/
Modified: 2013-02-12 - 22KB
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22: Method of placing source contacts for efficient EDS\EOS protection...
Method of placing source contacts for efficient EDS\EOS protection in grounded substrate MOS integrated circuit Application Type: Divisional Patent Number: 5468667 Country: United ...
URL: https://www.src.org/library/patent/p0373/
Modified: 1995-11-21 - 22KB
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23: System and Method to Test Integrated Circuits on a Wafer (Patent...
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URL: https://www.src.org/library/patent/p0413/
Modified: 2008-01-29 - 22KB
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24: Method and Apparatus For Rapidly Modeling and Simulating Intra...
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URL: https://www.src.org/library/patent/p1160/
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25: Methods for Characterizing, Generating Test Sequences for, and...
Methods for Characterizing, Generating Test Sequences for, and Simulating Integrated Circuit Faults Using Fault Tuples and Related Systems and Computer Program Products Application ...
URL: https://www.src.org/library/patent/p0228/
Modified: 2004-12-28 - 22KB
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26: Method for Testing Analog and Mixed-Signal Circuits Using Dynamic...
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URL: https://www.src.org/library/patent/p0468/
Modified: 2009-09-08 - 23KB
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27: pdfSRC/NSF Design Forum - Position Statement
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URL: https://www.src.org/...764/jason-cong-position-statement.pdf
Modified: 2011-08-02 - 35KB
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28: Retiming-Based Design Flow for Delay Recovery on Inter-Die Paths...
Retiming-Based Design Flow for Delay Recovery on Inter-Die Paths in 3D ICs Application Type: Utility Patent Number: 8832608 Country: United States Status: Filed on 17-Jun-2013, ...
URL: https://www.src.org/library/patent/p1411/
Modified: 2014-09-09 - 22KB
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29: Method, Apparatus and Computer Program Product for Determining...
Method, Apparatus and Computer Program Product for Determining a Frequency Domain Response of a Nonlinear Microelectronic Circuit Application Type: Utility Patent Number: 5663890 ...
URL: https://www.src.org/library/patent/p0014/
Modified: 1997-09-02 - 24KB
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30: Scan Test of Die Logic in 3D ICs Using TSV Probing (Patent P1368...
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URL: https://www.src.org/library/patent/p1368/
Modified: 2014-07-15 - 22KB
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1 through 30 of 83 similar documents, best matches first.   
Results by:Thunderstone Page: 1 2 3 next >>