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- 1: ESD/EOS Protection Circuits for Integrated Circuits (Patent P0074...
- ESD/EOS Protection Circuits for Integrated Circuits Application Type: Utility Patent Number: 5450267 Country: United States Status: Filed on 31-Mar-1993, Issued on 12-Sep-1995, ...
URL: https://www.src.org/library/patent/p0074/
Modified: 1995-09-12 - 25KB
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- 2: Source Contact Placement for Efficient ESD/EOS Protection in...
- Source Contact Placement for Efficient ESD/EOS Protection in Grounded Substrate MOS Integrated Circuit Application Type: Utility Patent Number: 5404041 Country: United States ...
URL: https://www.src.org/library/patent/p0067/
Modified: 1995-04-04 - 25KB
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- 3: Methods, Apparatus and Computer Program products for Synthesizing...
- Methods, Apparatus and Computer Program products for Synthesizing Integrated Circuits with Electrostatic Discharge Capability and Correcting Ground Rule Faults Therein Application ...
URL: https://www.src.org/library/patent/p0049/
Modified: 1998-08-18 - 27KB
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- 4: Method of placing source contacts for efficient EDS\EOS protection...
- Method of placing source contacts for efficient EDS\EOS protection in grounded substrate MOS integrated circuit Application Type: Divisional Patent Number: 5468667 Country: United ...
URL: https://www.src.org/library/patent/p0373/
Modified: 1995-11-21 - 22KB
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- 5: Method, Apparatus and Computer Program Product for Determining...
- Method, Apparatus and Computer Program Product for Determining a Frequency Domain Response of a Nonlinear Microelectronic Circuit Application Type: Utility Patent Number: 5663890 ...
URL: https://www.src.org/library/patent/p0014/
Modified: 1997-09-02 - 24KB
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- 6: Testing Monolithic Three Dimensional Integrated Circuits (Patent...
- Testing Monolithic Three Dimensional Integrated Circuits Application Type: Utility Patent Number: 10775429 Country: United States Status: Filed on 2-Nov-2017, Issued on 15-Sep-2020 ...
URL: https://www.src.org/library/patent/p1746/
Modified: 2020-09-15 - 25KB
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- 7: Multi-Layer Integrated Circuits Having Isolation Cells for Layer...
- Multi-Layer Integrated Circuits Having Isolation Cells for Layer Testing and Related Methods Application Type: Continuation (in part) Patent Number: 10838003 Country: United States ...
URL: https://www.src.org/library/patent/p1826/
Modified: 2020-11-17 - 25KB
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- 8: Multi-Layer Integrated Circuits Having Isolation Cells for Layer...
- Multi-Layer Integrated Circuits Having Isolation Cells for Layer Testing and Related Methods Application Type: Utility Patent Number: 10338133 Country: United States Status: Filed ...
URL: https://www.src.org/library/patent/p1639/
Modified: 2019-07-02 - 25KB
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- 9: Method and Apparatus for Sampling and Predicting Rare Events...
- Method and Apparatus for Sampling and Predicting Rare Events in Complex Electronic Devices, Circuits and Systems Application Type: Utility Patent Number: 8155938 Country: United ...
URL: https://www.src.org/library/patent/p1078/
Modified: 2012-04-10 - 24KB
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- 10: Wire Width Planning and Performance Optimization for VLSI Interconnect...
- Wire Width Planning and Performance Optimization for VLSI Interconnects Application Type: Utility Patent Number: 6408427 Country: United States Status: Filed on 22-Feb-2000, Issued ...
URL: https://www.src.org/library/patent/p0001/
Modified: 2002-06-18 - 29KB
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- 11: Characterization Of Radio Frequency (RF) Signals Using Wavelet...
- Characterization Of Radio Frequency (RF) Signals Using Wavelet-Based Parameter Extraction Application Type: Utility Patent Number: 7340381 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p0325/
Modified: 2008-03-04 - 23KB
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- 12: Software-Based Self-Test and Diagnosis Using on-Chip Memory ...
- Software-Based Self-Test and Diagnosis Using on-Chip Memory Application Type: Divisional Patent Number: 10788532 Country: United States Status: Filed on 30-Nov-2017, Issued on ...
URL: https://www.src.org/library/patent/p1753/
Modified: 2020-09-29 - 26KB
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- 13: Software-Based Self-Test and Diagnosis Using on-Chip Memory ...
- Software-Based Self-Test and Diagnosis Using on-Chip Memory Application Type: Divisional Patent Number: 10845416 Country: United States Status: Filed on 30-Nov-2017, Issued on ...
URL: https://www.src.org/library/patent/p1752/
Modified: 2020-11-24 - 26KB
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- 14: Software-Based Self-Test and Diagnosis Using On-Chip Memory ...
- Software-Based Self-Test and Diagnosis Using On-Chip Memory Application Type: Utility Patent Number: 9864007 Country: United States Status: Filed on 30-Apr-2014, Issued on ...
URL: https://www.src.org/library/patent/p1457/
Modified: 2018-01-09 - 25KB
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- 15: Cell-Level Signal Electromigration (Patent P1459) - SRC
- Cell-Level Signal Electromigration Application Type: Utility Patent Number: 9665680 Country: United States Status: Filed on 30-May-2014, Issued on 30-May-2017 Organization: ...
URL: https://www.src.org/library/patent/p1459/
Modified: 2017-05-30 - 22KB
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- 16: Configurable Circuits Using Phase Change Switches (Patent P0534...
- Configurable Circuits Using Phase Change Switches Application Type: Utility Patent Number: 7634248 Country: United States Status: Filed on 1-Aug-2006, Issued on 15-Dec-2009, Patent ...
URL: https://www.src.org/library/patent/p0534/
Modified: 2009-12-15 - 22KB
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- 17: Method and Architecture for Pre-bond Probing of TSVs in 3D Stacked...
- Method and Architecture for Pre-bond Probing of TSVs in 3D Stacked Integrated Circuits Application Type: Utility Patent Number: 8775108 Country: United States Status: Filed on ...
URL: https://www.src.org/library/patent/p1291/
Modified: 2014-07-08 - 22KB
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- 18: Method and System for Synthesizing Relative Timing Constraints...
- Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design to Facilitate Timing Verification Application Type: Continuation Patent Number: ...
URL: https://www.src.org/library/patent/p1354/
Modified: 2012-11-27 - 24KB
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- 19: Method and System for Synthesizing Relative Timing Constraints...
- Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design to Facilitate Timing Verification Application Type: Utility Patent Number: 8239796 ...
URL: https://www.src.org/library/patent/p1202/
Modified: 2012-08-07 - 24KB
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- 20: Built-in Current Testing of Integrated Circuits (Patent P0109...
- Built-in Current Testing of Integrated Circuits Application Type: Utility Patent Number: 5025344 Country: United States Status: Filed on 22-Feb-1990, Issued on 18-Jun-1991, Patent ...
URL: https://www.src.org/library/patent/p0109/
Modified: 1991-06-18 - 22KB
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- 21: Systems, Methods and Computer Program Products for Creating Hierarchic...
- Systems, Methods and Computer Program Products for Creating Hierarchical Equivalent Circuit Models Application Type: Utility Patent Number: 7096174 Country: United States Status: ...
URL: https://www.src.org/library/patent/p0200/
Modified: 2006-08-22 - 24KB
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- 22: Embedded IC Test Circuits and Methods (Patent P0525) - SRC
- Embedded IC Test Circuits and Methods Application Type: Utility Patent Number: 7379716 Country: United States Status: Filed on 24-Mar-2005, Issued on 27-May-2008, Patent Abandoned ...
URL: https://www.src.org/library/patent/p0525/
Modified: 2008-05-27 - 23KB
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- 23: Systems and Methods for Testing Integrated Circuits (Patent P0342...
- Systems and Methods for Testing Integrated Circuits Application Type: Utility Patent Number: 7032151 Country: United States Status: Filed on 13-Nov-2002, Issued on 18-Apr-2006, ...
URL: https://www.src.org/library/patent/p0342/
Modified: 2006-04-18 - 22KB
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- 24: Method of Fabricating a Self-Aligned High Speed MOSFET Device...
- Method of Fabricating a Self-Aligned High Speed MOSFET Device Application Type: Continuation (in part) Patent Number: 5599728 Country: United States Status: Filed on 28-Oct-1994, ...
URL: https://www.src.org/library/patent/p0006/
Modified: 1997-02-04 - 22KB
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- 25: Scan Test of Die Logic in 3D ICs Using TSV Probing (Patent P1368...
- Scan Test of Die Logic in 3D ICs Using TSV Probing Application Type: Utility Patent Number: 8782479 Country: United States Status: Filed on 1-Nov-2012, Issued on 15-Jul-2014, ...
URL: https://www.src.org/library/patent/p1368/
Modified: 2014-07-15 - 22KB
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- 26: System and Method to Test Integrated Circuits on a Wafer (Patent...
- System and Method to Test Integrated Circuits on a Wafer Application Type: Utility Patent Number: 7325180 Country: United States Status: Filed on 26-Nov-2003, Issued on ...
URL: https://www.src.org/library/patent/p0413/
Modified: 2008-01-29 - 22KB
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- 27: Method for Testing Analog and Mixed-Signal Circuits Using Functionally...
- Method for Testing Analog and Mixed-Signal Circuits Using Functionally Related Excitations and Functionally Related Measurements Application Type: Utility Patent Number: 7129734 ...
URL: https://www.src.org/library/patent/p0458/
Modified: 2006-10-31 - 25KB
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- 28: Method and Apparatus For Rapidly Modeling and Simulating Intra...
- Method and Apparatus For Rapidly Modeling and Simulating Intra-Die Statistical Variations in Integrated Circuits using Compressed Parameter Models Application Type: Utility Patent ...
URL: https://www.src.org/library/patent/p1160/
Modified: 2012-10-16 - 24KB
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- 29: Methods, Systems, and Computer Program Products for Modeling...
- Methods, Systems, and Computer Program Products for Modeling inductive Effects in a circuit combing a plurality of localized models Application Type: Utility Patent Number: 6820245 ...
URL: https://www.src.org/library/patent/p0251/
Modified: 2004-11-16 - 23KB
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- 30: Retiming-Based Design Flow for Delay Recovery on Inter-Die Paths...
- Retiming-Based Design Flow for Delay Recovery on Inter-Die Paths in 3D ICs Application Type: Utility Patent Number: 8832608 Country: United States Status: Filed on 17-Jun-2013, ...
URL: https://www.src.org/library/patent/p1411/
Modified: 2014-09-09 - 22KB
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